1. Field of the Invention
This invention generally relates to the field of electrostatic discharge (ESD) protection of a metal oxide semiconductor (MOS). More particularly, the present invention relates to ESD protection of a BiCMOS.
2. Description of the Prior Art
An ESD event is the main reason resulting in the majority of electronic parts or systems damaged by an electrostatic overstress (EOS). This kind of damage makes semiconductor parts and computer systems damaged forever, affecting the functionalities of integrated circuits (ICs), and causes electronic products work abnormally. However, the damage caused from ESD is mostly produced by human beings, and is also difficult to avoid. Electrostatic energy can accumulate in human beings, apparatuses, storing devices, and even electronic parts or systems themselves during the processes of manufacture, assembly, testing, storage and shipping. Without the desire, people provide a discharge path by contacting those objects to each other and damage the electronic parts or systems by an ESD event.
According to the produced reasons and discharging methods to ICs, electrostatic energy can be categorized into four categories: human-body model (HBM), machine model (MM), charged-device model (CDM), and field-induced model (FIM). Take HBM for example, a business IC has 2000V ESD voltages and assuming an equivalent body resistance of a human being is 1500 Ω, and hence the ESD current is about 1.3 amps. Therefore, an ESD protecting circuit is fabricated within an IC in order to protect the IC from the ESD damage. The ESD protecting circuit is a special circuit for ESD protection, providing an ESD path for discharge current, and keeps the discharge current from flowing into the inner circuit of the IC to cause damage. The ESD of both HBM and MM is caused from external environments, and hence ESD protecting circuits are fabricated beside pads. Those output pads of PMOS and NMOS with big dimensions could be used as ESD protecting parts. Since the input pads of CMOS ICs are commonly connected with the gates of MOS parts and the gate oxide layer is the easiest to be penetrated by an ESD, a set of ESD protecting circuit is fabricated beside the input pads to protect the input parts. The ESD protecting circuits are also fabricated beside the pads of VDD and VSS since both of them may be discharged by ESD events.
A traditional ESD protecting circuit of a MOS is shown in FIG. 1A, where the general triggering voltage of the MOS 10 is around 10V. While the voltage across the MOS 10 exceeds 10V, the MOS enters a snapback region that leads electrostatic charges out to protect the inner circuit from excessive voltage and ESD current. As shown in FIG. 1B, while the voltage V of the parasitic BJT 12 of the MOS 10 (shown in FIG. 1A) reaches Vt1, the MOS 10 enters a snapback region, and further, if the current reaches It2, the MOS 10 is burned out. By insuring that the voltage across the MOS 10 stops rising while the MOS 10 is in a snapback region, better ESD protection can be achieved.
The CMOS technique plays a main role in the semiconductor IC so far. As the manufacture processes of the CMOS IC have been gradually evolving, the dimensions of the parts have been scaled into deep-submicron to improve the performance of ICs and the operation speed, and to reduce the manufacture cost for each chip. However, the technique of advanced process mentioned above and the smaller scaled parts can make the submicron CMOS ICs reduce the capability of ESD protection, and on the other hand, electrostatic produced by external environments is still the same as before. Hence, the CMOS ICs damaged by ESD become more serious and many submicron CMOS ICs all face the same thorny problem.
To improve the performance of the ESD protecting circuit, the breakdown voltage of a zener diode is used to bias the gate or the substrate electrode of the MOS 10, as shown in FIG. 1C and FIG. 1D, thus causing the MOS to lead electrostatic charge out across a low voltage. However, the doped concentration has to be increased to achieve a zener diode with a lower breakdown voltage, and this can cause a leakage current problem. As shown in FIG. 1E, an RC circuit can be utilized to trigger the MOS 10 but the cycle of the RC circuit is longer than the cycle of ESD (take HBM for example, about 150 μs), and also results in an undue layout area. The IBM company has recently announced a SiGe heterojunction bipolar transistor (HBJ) ESD protecting circuit in the ESD Association, as shown in FIG. 1F, where a BJT that is utilized to solve the leakage current problem instead of a zener diode.
In view of the drawbacks mentioned with the prior art of ESD protection, there is a continued need to develop new and improved ESD protection that overcomes the disadvantages associated with the prior art of ESD protection.